In recent years, advancements have continued to be made in size and weight reduction, high performance and high functionality of devices such as personal computers, cellular phones, wireless base stations, optical communication devices, servers and routers, of various sizes. Development of high-density mounting techniques for System-on-Chips (SoC) and System-in-Packages (SiP) is also progressing with increasing LSI speeds and functionality for CPU, DSP and memory devices.
Build-up system-type multilayer circuit boards are therefore being employed on semiconductor chip mounting boards and motherboards. With advancements in mounting technologies such as multi-pin and narrow-pitch formation on packages, printed circuit boards have been shifting from QFP (Quad Flat Package) to BGA (Ball Grid Array)/CSP (Chip Size Package) mounting.
Connection between semiconductor chip mounting boards and semiconductor chips is accomplished using gold wire bonding, for example. Semiconductor packages comprising connected semiconductor chip mounting boards and semiconductor chips are also connected with circuit boards (motherboards) by solder balls. Semiconductor chip mounting boards usually have connecting terminals for connection with semiconductor chips or circuit boards. Most connecting terminals are gold plated to ensure satisfactory metal bonding with gold wire or solder.
Electrolytic gold plating has been widely employed in the prior art as a method of gold plating connecting terminals. However, with the increasing high density of wirings due to smaller semiconductor packages, it is becoming difficult to secure the wirings for forming electrolytic gold plating on connecting terminal surfaces. Electroless gold plating processes, which do not require special wiring, have begun to receive attention, and Patent document 1, for example, proposes a process in which a copper circuit is plated by electroless nickel plating and then electroless gold plating. The term “electroless gold plating” referred to here means “displacement plating alone” or “displacement plating and electroless plating (reduction plating with a reducing agent in the plating solution).
Patent document 2, on the other hand, examines formation of an electroless nickel plating film, electroless palladium plating film, displacement gold plating film and electroless gold plating film in that order on the surface of copper in the shape of a terminal, because the wire bonding strength between the metal terminal and gold wire is reduced when a displacement or electroless gold plating film is formed after formation of an electroless nickel plating film, due to the heat treatment that follows plating. In Non-patent document 1, there is reported formation of an electroless palladium plating film as a phosphorus-containing electroless palladium-phosphorus alloy plating film using an electroless palladium plating solution with hypophosphorous acid or phosphorous acid as the reducing agent, to obtain a plating film formed by electroless nickel plating, electroless palladium-phosphorus plating and gold plating.
[Patent document 1] Japanese Patent Application Laid-Open HEI No. 5-343834
[Patent document 2] Japanese Patent Publication No. 3596335
[Non-patent document 1] Hyoumen Gijutsu [Surface Techniques]; 58, 35 (2007)